Unive VLSI Lab
The definitive resource for Silicon Engineering. Access peer-reviewed whitepapers, RTL-to-GDSII skill guides, and expert-authored VLSI textbooks.
From Specification to Tape-out
VLSI design is a multi-stage process requiring precision at every node. Our content is organized following the standard industry EDA flow, ensuring you learn the tools and methodologies used at Tier-1 semiconductor firms.
- Front-end RTL
- Synthesis
- DFT Insertion
- Physical Design
- Sign-off
- Post-Silicon
ASIC Physical Design &
Floorplanning
Partitioning & Floorplanning
Defining the core area, aspect ratio, and I/O placement while managing power grid distribution.
Placement & CTS
Automated cell placement followed by Clock Tree Synthesis (CTS) to minimize skew and latency.
Routing & DRC/LVS
Detail routing and final verification to ensure the layout matches the netlist and fabrication rules.
Resource Summary
Latest Research & Literature
CMOS Analog IC Design
A deep dive into operational amplifiers, bandgap references, and data converters using modern CMOS processes.
The Shift to Chiplet Architecture
An industry report on the economic and technical transition from monolithic SoC to heterogenous chiplet integration.
Static Timing Analysis (STA) Mastery
Complete roadmap to mastering setup/hold constraints, false paths, and multi-mode multi-corner (MMMC) analysis.